Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
One type of smaller packages for semiconductor devices that has been developed is the wafer level package (WLP), in which integrated circuits are packaged in packages that typically include a redistribution layer (RDL) or post-passivation interconnect (PPI) that is used to fan out wires for contact pads of the circuit so that electrical contacts can be made on a larger pitch than contact pads of the circuit.
WLP packages have been applied more and more in integrated circuit packaging due to the advantages of cost and simple structure. However, the standard manufacture process for WLP is expensive, which may need four photo masks. In addition, non-optimized solder flux amount used during the mounting of the solder balls on the RDL or the PPI on the wafer can cause the solder balls not to be firmly connected. Methods and systems to solve those problems are needed.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.